The microcontroller with your own hands
Trying to learn the controllers and already possessing the skills of programming the FPGA, I came up with a stupid idea. Came, knocked, and entered. To all those who come bad thoughts, and it is interesting how this phenomenon consult others dedicated.
The idea to paint your controller, not limited by the number of peripherals, RAM, and other parameters, in addition to the capacity of the FPGA. For example the controller contains 5 UARTов, and desperately need a sixth, you will have to Dodge. But what if you could just click and add necessary? Or Vice versa, the task is well solved in the five controllers with the bit 5, 32, 20, 32 and 20 with an unpredictable number of communication lines between them. Sorry to use five 32 arresters, life is always a pity, but to combine the two subtasks per core – ugly or something.
The response time to the interrupt in the controller is sufficiently large. Yes, the interrupt controller monitors the inputs of the (somehow limited) regardless of the kernel. But before starting the code execution of the program for processing an interrupt, for example, to read the port, you want to save the General purpose registers, and then they still have to recover. And it's not a beat on an empty from the point of view of logic of the program re-writing registers on the stack and return the same values back. It certainly fits into the concept of real time, but you can also do it instantly: executed code with low priority, on the following clock cycle because of the sharp necessity begins to run a high-priority timer interrupt, and a quantum code is executed by processing an external data stream, because there is absolutely everything you need to quickly.
Of course, all these issues decided and resolved and easily and simply. But bad idea is not looking for such solutions, she's just walking around in a crowded space of mind and pushes you to do something extraordinary. And if the young engineer leave, then I'm sorry his wife and children, but the Pope is not "again sitting at the computer", and growing professionally. Moreover, sometimes you want to run not someone come up with puzzles, and his, fully his.
Fig. 1. Timers. Add as many you want. Please note the grammatical error. A shame, but do not want the Builder to install to recompile.
Let me introduce you to the controller, whose architecture is not that different from all the others, rather she adopted. Have long forgotten the list read before the beginning of works of literature, used the thoughts of many people from different computing eras, forgive me my neglected master. But you don't have to disown me. And money is not brought, therefore, to share nothing.
I must say that the controller was held, stitched in Spartana all generations and successfully working in the CIS and one of the Baltic countries. Now would a lot was done differently, but any changes I'm already lazy and what happened, happened. What happened was this.
— The bit depth of the controller from 1 to 32, with a sign or without it. (I don't remember checked I work on small bit). Use additional code.
— The number of ports I/o is not restricted, the bit width is limited by the bit width of the kernel.
— The number of timers is not limited. For each timer you can set your interrupt handler.
— The interrupt handler with an infinite number of inputs, each input has a priority from 0 to 99 (limitation due to "and so a large number"). The ability to prevent all interrupts, or only a low priority.
— Number of serial ports, the type UART unlimited, the bit width is limited by the bit width of the kernel.
— The frequency divider is done poorly and wrong, but regularly generates any frequency for any of the periphery or just outside of the controller.
— Coprocessor. Read about it below.
That is, we have a controller that supports basic arithmetic operations and other changes bits in the words (plus, minus, shift, bitwise logic...). He also refers to the internal memory and stores program code are also within yourself. The memory block is used, it is the platform and in the settings it is necessary to specify what kind of chip will be a carrier of the controller. All operations on any course of action are performed in one clock cycle, it may not always a good thing, but simplified design architecture. The exception is the integer divider, which is implemented in the coprocessor, the division is performed slowly but surely. The division algorithm was chosen as the easiest bit.
I would like to tell you about the code of the teams, but I do not remember what it consists of. Based on the principle of "not to use what is not used" even long the command code value is not constant, the more its contents. For example, if the compiled program is found 14 teams, each team coded 4 bits, if you use 18 teams – the fifth bit is allocated. Plus, each team are added a bit long, if it is 0, the command single if 1 – double, or Vice versa, it doesn't matter. Double-team needed for operations, contains the address of RAM or ROM. Add to this the fact that the address bus also have non-constant length, and get a complete mess in your code commands to consider it in any disassembler makes no sense, as the actual assembler in this controller.
The Fort here is the language that enabled me to develop these strange ideas. Fort simple and low level. Writing a compiler of this language a pleasure. Well, of course, all language constructs are not supported, only basic data forwarding and change them.
Fig. 2. The user is quite modest. Immodest and not written.
Fig. 3. The second part of the guide. I don't know why, but the window can not expand. There is a third part, but really quite boring.
And, of course, we have the stack controller. That is, the Fort functioned in its natural environment – in the stack, hardware stack, not slow software. "All over the beat!" the second motto of the project. Hardware stack enabled upon the transition in the function or call interrupt immediately proceed to the command execution processing of the data, without the need to store content of the interrupted process. The "new" data is simply placed on the stack top, the "old" go back there and perfectly preserved. Then the "new" data by participating in different operations, successfully transferred to RAM or other places and "old" are pushed to the top. When returning to the interrupted piece of code, no one will notice. The address of the interrupted code is stored in another stack, and the maximum number of aborted processes depends only from the Stack depth Returns. This value is configurable at compile time, even if "very large number". Parameters to functions are passed via the stack.
Stackcpu – it's called a controller, for some reason, the Latin alphabet, but to write code and Cyrillic. What I do, I will give an example of the function "Menyailo":
the
Where: "cidaemon", "меняем_прочитанное_из_нужного_порта", "записываем_в_требуемую_ячейку_памяти" — functions that perform certain actions.
Well, notif I'm crazy beautifully? I will cite the evidence, the program control the traffic lights:
the
Well,psycho beautiful? The third principle of the project "Literary language in the management of the electronics!" Although, as shown, to write so the program is quite tedious. For connoisseurs of the Fort reported that point my compiler interprets as a delimiter, and a comma too. Of course, it is better to use the language, but the compiler With my teeth, and use third-party compilers architecture does not allows.
Fig. 4. Development environment with the report compiler and the linker.
How much capacity FPGA is the controller? Well, who knows. It all depends on the bit number of the selected peripheral, something else, and the text of the program. The controller will not be a multiplier if it is not found in the code or there is no divider, if it is not used by the programmer. Under programmer I mean me, since other programmers of the controller does not exist (the principle of "do not use for those who do not use"). According to the block of memory to RAM data and ROM teams: at least two block, high block, the entire memory chip.
The maximum frequency is calculated experimentally, for a specific architecture. One of my 24 bit controllers are not operated at a frequency of 48 Mhz Spartan2, at a frequency of 40Mhz earned. In Spartan6 on the hundred Mhz 32-bit worked. And maybe on a couple of hundred will work, it's so complicated.
Fig. 5. This code will see the processor. Please note, one team FORTH is one command of the processor core – single system clock.
First PS: I will mention one possibility of the co – filter. Conventional IIR filter. But what is unusual about it is that it uses floating point. Not that this was some kind of meaning, just read a book about the presentation of the numbers, and decided:nonsense interesting that your floating point will do.
Fig. 6. The simulation results of the filter operation. Calculated logic VHDL code with the accuracy up to bitica.
Also had plans on turning the project in system-on-chip: the addition of a different, written in VHDL blocks in the periphery of the controller. And it seems not so difficult, but the fuse has dried up. The bad thoughts left me, and roam somewhere between programmers and electrical engineers. And call them now Startups.
So, if to you someone will come and will have a Startup, think, and do not hiding underneath any Primaeval.
And another PS: on the other hand, during the work on the project Stackcpu I did learn somethree programming language:
1. FORTH, or rather some of its subset that is required to test the functionality of the controller.
2. C++, pure C, it would be hard to write a development environment and compiler.
3. VHDL, the letters of this language are the controller.
It is clear that to be a long talk, but enough is enough. Going to do other people's ideas, but with my implementation!
Actually the controller (half a megabyte): cloud.mail.ru/public/1cdf4b1d4799/StackCPU.rar
Article based on information from habrahabr.ru
The idea to paint your controller, not limited by the number of peripherals, RAM, and other parameters, in addition to the capacity of the FPGA. For example the controller contains 5 UARTов, and desperately need a sixth, you will have to Dodge. But what if you could just click and add necessary? Or Vice versa, the task is well solved in the five controllers with the bit 5, 32, 20, 32 and 20 with an unpredictable number of communication lines between them. Sorry to use five 32 arresters, life is always a pity, but to combine the two subtasks per core – ugly or something.
The response time to the interrupt in the controller is sufficiently large. Yes, the interrupt controller monitors the inputs of the (somehow limited) regardless of the kernel. But before starting the code execution of the program for processing an interrupt, for example, to read the port, you want to save the General purpose registers, and then they still have to recover. And it's not a beat on an empty from the point of view of logic of the program re-writing registers on the stack and return the same values back. It certainly fits into the concept of real time, but you can also do it instantly: executed code with low priority, on the following clock cycle because of the sharp necessity begins to run a high-priority timer interrupt, and a quantum code is executed by processing an external data stream, because there is absolutely everything you need to quickly.
Of course, all these issues decided and resolved and easily and simply. But bad idea is not looking for such solutions, she's just walking around in a crowded space of mind and pushes you to do something extraordinary. And if the young engineer leave, then I'm sorry his wife and children, but the Pope is not "again sitting at the computer", and growing professionally. Moreover, sometimes you want to run not someone come up with puzzles, and his, fully his.
Fig. 1. Timers. Add as many you want. Please note the grammatical error. A shame, but do not want the Builder to install to recompile.
Let me introduce you to the controller, whose architecture is not that different from all the others, rather she adopted. Have long forgotten the list read before the beginning of works of literature, used the thoughts of many people from different computing eras, forgive me my neglected master. But you don't have to disown me. And money is not brought, therefore, to share nothing.
I must say that the controller was held, stitched in Spartana all generations and successfully working in the CIS and one of the Baltic countries. Now would a lot was done differently, but any changes I'm already lazy and what happened, happened. What happened was this.
— The bit depth of the controller from 1 to 32, with a sign or without it. (I don't remember checked I work on small bit). Use additional code.
— The number of ports I/o is not restricted, the bit width is limited by the bit width of the kernel.
— The number of timers is not limited. For each timer you can set your interrupt handler.
— The interrupt handler with an infinite number of inputs, each input has a priority from 0 to 99 (limitation due to "and so a large number"). The ability to prevent all interrupts, or only a low priority.
— Number of serial ports, the type UART unlimited, the bit width is limited by the bit width of the kernel.
— The frequency divider is done poorly and wrong, but regularly generates any frequency for any of the periphery or just outside of the controller.
— Coprocessor. Read about it below.
That is, we have a controller that supports basic arithmetic operations and other changes bits in the words (plus, minus, shift, bitwise logic...). He also refers to the internal memory and stores program code are also within yourself. The memory block is used, it is the platform and in the settings it is necessary to specify what kind of chip will be a carrier of the controller. All operations on any course of action are performed in one clock cycle, it may not always a good thing, but simplified design architecture. The exception is the integer divider, which is implemented in the coprocessor, the division is performed slowly but surely. The division algorithm was chosen as the easiest bit.
I would like to tell you about the code of the teams, but I do not remember what it consists of. Based on the principle of "not to use what is not used" even long the command code value is not constant, the more its contents. For example, if the compiled program is found 14 teams, each team coded 4 bits, if you use 18 teams – the fifth bit is allocated. Plus, each team are added a bit long, if it is 0, the command single if 1 – double, or Vice versa, it doesn't matter. Double-team needed for operations, contains the address of RAM or ROM. Add to this the fact that the address bus also have non-constant length, and get a complete mess in your code commands to consider it in any disassembler makes no sense, as the actual assembler in this controller.
The Fort here is the language that enabled me to develop these strange ideas. Fort simple and low level. Writing a compiler of this language a pleasure. Well, of course, all language constructs are not supported, only basic data forwarding and change them.
Fig. 2. The user is quite modest. Immodest and not written.
Fig. 3. The second part of the guide. I don't know why, but the window can not expand. There is a third part, but really quite boring.
And, of course, we have the stack controller. That is, the Fort functioned in its natural environment – in the stack, hardware stack, not slow software. "All over the beat!" the second motto of the project. Hardware stack enabled upon the transition in the function or call interrupt immediately proceed to the command execution processing of the data, without the need to store content of the interrupted process. The "new" data is simply placed on the stack top, the "old" go back there and perfectly preserved. Then the "new" data by participating in different operations, successfully transferred to RAM or other places and "old" are pushed to the top. When returning to the interrupted piece of code, no one will notice. The address of the interrupted code is stored in another stack, and the maximum number of aborted processes depends only from the Stack depth Returns. This value is configurable at compile time, even if "very large number". Parameters to functions are passed via the stack.
Stackcpu – it's called a controller, for some reason, the Latin alphabet, but to write code and Cyrillic. What I do, I will give an example of the function "Menyailo":
the
:meniailo
citaient,
меняем_прочитанное_из_нужного_порта,
записываем_в_требуемую_ячейку_памяти;
Where: "cidaemon", "меняем_прочитанное_из_нужного_порта", "записываем_в_требуемую_ячейку_памяти" — functions that perform certain actions.
Well, not
the
\\main
BEGIN
green extinguished yellow extinguished, red light.
fifty seconds of waiting...
green put out, yellow light, red extinguished.
four seconds of waiting...
green light, yellow to extinguish, to put out red.
forty seconds waiting...
amenitities green, yellow, burn, and red Negoro.
four seconds of waiting...
0 UNTIL \an infinite loop
Well,
Fig. 4. Development environment with the report compiler and the linker.
How much capacity FPGA is the controller? Well, who knows. It all depends on the bit number of the selected peripheral, something else, and the text of the program. The controller will not be a multiplier if it is not found in the code or there is no divider, if it is not used by the programmer. Under programmer I mean me, since other programmers of the controller does not exist (the principle of "do not use for those who do not use"). According to the block of memory to RAM data and ROM teams: at least two block, high block, the entire memory chip.
The maximum frequency is calculated experimentally, for a specific architecture. One of my 24 bit controllers are not operated at a frequency of 48 Mhz Spartan2, at a frequency of 40Mhz earned. In Spartan6 on the hundred Mhz 32-bit worked. And maybe on a couple of hundred will work, it's so complicated.
Fig. 5. This code will see the processor. Please note, one team FORTH is one command of the processor core – single system clock.
First PS: I will mention one possibility of the co – filter. Conventional IIR filter. But what is unusual about it is that it uses floating point. Not that this was some kind of meaning, just read a book about the presentation of the numbers, and decided:
Fig. 6. The simulation results of the filter operation. Calculated logic VHDL code with the accuracy up to bitica.
Also had plans on turning the project in system-on-chip: the addition of a different, written in VHDL blocks in the periphery of the controller. And it seems not so difficult, but the fuse has dried up. The bad thoughts left me, and roam somewhere between programmers and electrical engineers. And call them now Startups.
So, if to you someone will come and will have a Startup, think, and do not hiding underneath any Primaeval.
And another PS: on the other hand, during the work on the project Stackcpu I did learn some
1. FORTH, or rather some of its subset that is required to test the functionality of the controller.
2. C++, pure C, it would be hard to write a development environment and compiler.
It is clear that to be a long talk, but enough is enough. Going to do other people's ideas, but with my implementation!
Actually the controller (half a megabyte): cloud.mail.ru/public/1cdf4b1d4799/StackCPU.rar
